PLATON: Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects

[January 2010 – December 2012]

Overview of PLATON

PLATON aimed to address the size and power consumption bottleneck in Data Centers and High-Performance Computing Systems (HPCS) by realizing chip-scale high-throughput routing fabrics with reduced energy consumption and footprint requirements. It intended to demonstrate Tb/s optical router prototypes for optical interconnects adopting plasmonics as its disruptive technology to reduce size and energy values. To achieve this, PLATON intended to deploy innovative plasmonic structures for switching applications and to develop novel fabrication processes for merging plasmonics with silicon nanophotonics and electronics. The enhanced functionality of PLATON’s platform was utilized to develop and demonstrate Tb/s routing, enabling the penetration of a merged plasmonics/photonics configuration in short-range blade and backplane data interconnects. PLATON’s optical board technology was expected to blend the functional potential of small-footprint, high-bandwidth plasmonic structures and the integration potential of plasmonics with the more mature SOI technology providing a new generation of miniaturized photonic components. Its main objectives span along the fabrication and demonstration of:

  1. a whole new series of 2×2 plasmonic switches with ultra-small footprint, very low power consumption and less than 1μsec switching times,
  2. a low latency, small-footprint 4×4 plasmonic thermooptic switch,
  3. an optically addressable plasmonic 1×2 switch capable of operating at bitrates in excess of 10Gb/s, and
  4. A 2×2 and a 4×4 Tb/s optical routing platforms relying on SOI motherboard hosting the plasmonic switching matrix and the IC header processor for application in optical blade and backplane interconnects.

System-level integration involved the demonstration of the packaged Tb/s routing prototype offering minimum space requirements and up to 1.12Tb/s throughput. Its performance was evaluated in a real WDM 40 Gb/s testbed for optical interconnects.

Summary of PLATON context and objectives

PLATON addressed the interconnect problem in high bandwidth, parallel processing environments, adopting an optical interconnect approach and employing optical components based on surface plasmon polaritons to overcome the traditional shortcomings of optics. PLATON introduced the following innovations:

Innovation 1: Advanced DLSPP waveguide engineering

  • Fiber-pigtailing of DLSPP waveguides: PLATON developed a novel butt-coupling technique that provided the first reported pigtailed DLSPP waveguides.
  • On-Chip Silicon-to-DLSPP coupling: PLATON developed an efficient Si-to-DLSPP coupling technique to enable the hybrid integration of plasmonic waveguide elements on silicon-on-insulator (SOI) boards.
  • Advanced thermo-optic DLSPP waveguides: PLATON enhanced the thermooptic efficiency of plasmonic waveguides by involving dielectric materials (IPG and Cyclomer) of significantly higher thermooptic coefficients with respect to the respective coefficient of the so far used PMMA (at least three times higher).
  • Quantum Dot-doped DLSPP waveguides: PLATON pursued research towards next generation, all-optical high-speed DLSPP switching elements.

Innovation 2: Advanced DLSPP switch modules

  • System-qualified 2×2 DLSPP thermooptic switches: PLATON fabricated the first high-speed, ultra-compact thermooptic DLSPP switches. Three generations of 2×2 DLSPP switching modules realized.
  • System-qualified 4×4 DLSPP packet switching matrix: PLATON fabricated a multi-element 4×4 DLSPP switching matrix.
  • All-optical high-speed 1×2 DLSPP switch: PLATON designed and developed an all-optical DLSPP switch operating in the telecom wavelengths.

Innovation 3: Hybrid integration of Plasmonics/Silicon nanophotonics & electronic ICs

  • CMOS-compatible SOI motherboard for silicon/plasmonic/electronic heterointegration: PLATON developed a CMOS compatible application specific optical board setup that integrated silicon and plasmon waveguide elements.
  • Packaging and Fiber-pigtailing: PLATON developed a multi-fiber array coupling technique based on high-index grating vertical couplers for the straightforward pigtailing of the multiple input and output port waveguides of the hybrid photonic chips.

Innovation 4: Tb/s 2×2 & 4×4 DLSPP-based routing platforms for optical data interconnects

High capacity DLSPP-based optical routing platforms for BladeServer and backplane data interconnects: PLATON integrated the SOI motherboard with the DLSPP switching modules and the IC microelectronic circuit into a single system that performed Tb/s-throughput routing of 40Gb/s optical packets for data interconnect applications.

Summary of PLATON current state back-to-back with its objectives

Main Scientific and Technical (S&T) results and foregrounds

To accomplish its objectives, PLATON based the organisation of the necessary management and RTD around 7 work-packages (WPs) as shown in the Figure below.

WP2 – Design and Ongoing Evaluation of PLATON’s Platform

Workpackage objectives

WP2 was concerned with the detailed design of the plasmonic/silicon photonic components and subsystems, the SOI motherboard platform, the IC circuitry and the final Tb/s routing interconnection platform. The main objectives were:

  • To define PLATON’s interconnection and routing specifications
  • To specify the parameters and design the components of PLATON’s subsystems
  • To assess the performance of PLATON’s components and to identify the optimum configurations, through theoretical analysis and numerical simulation.
  • To fabricate and evaluate the system performance of first, state-of-the-art DLSPP and SOI structures
  • To provide the final specifications of the modules to be developed based on the simulation analysis and the performance evaluation of the test structures
  • To design the final platform layout and define the final system level experimental testbed specifications

Progress towards objectives detailed for each task

Design of the optical interconnection routing platform

Blue-print designs and the respective gds files have been generated for both the 2×2 and 4×4 PLATON router platforms. Data traffic formats have been defined and a WDM-based packet formatting was adopted with NRZ data signals at 40Gb/s per wavelength. The process flow for the heterointegration of PLATON’s photonics, plasmonics and electronics elements has been determined and has been also successfully applied in real prototypes. Both the 2×2 and the 4×4 router designs were evaluated by means of simulations with true data traffic patterns. An additional 2×2 router architecture has been designed and had its performance simulated, exploiting a dual-WRR plasmonic switch and leading to 320Gb/s (8x40Gb/s) switching capacity.

Figure 1-1 GDS layout of the 2x2 PLATON router
Figure 1-1 GDS layout of the 2x2 PLATON router
Figure 1-2 GDS layout of the 4x4 PLATON router
Figure 1-2 GDS layout of the 4x4 PLATON router

Design of Silicon Photonic components and RF/electronic circuitry

Specifications about all necessary non‐plasmonic subsystems and components have been defined and the respective device designs have been produced. In more detail:

8:1 SOI multiplexers have been designed in four different layouts for operation in four different spectral bands within the 1530-1565 nm wavelength window, offering 100GHz channel spacing and 40Gbps NRZ signal operation. 2nd order ring resonator structures were employed in the final layout with ring radii close to 9um and to 12um, equipped with heaters for allowing thermo-optical tuning of their resonances in order to accurately define the operating channels. Following the successful experimental confirmation of the SOI-MUX designs generated, this activity has verified the validity of a custom-made circuit-level simulation tool that optimally bridges electromagnetic simulations with system-level functionality towards designing circuits and subsystems with very low computational power.

Silicon-integrated photodiodes:  An all‐silicon implanted photodetector concept has been utilized for header detection and o/e conversion purposes, as this optimally compromises the router prototype needs for easy, cost-effective integration and low-rate header pulse detection. In this type of photodetectors, the generation of charge carriers relies on linear direct absorption at incorporated defect states, which constitute inter-band energy levels caused by silicon ion implantation. Respective designs have been created exploiting Si-rib waveguide structures and have been subsequently verified by experiments performed on fabricated devices, yielding operation at data rates higher than the 1MHz targeted within PLATON for its packet header sequences.

Passive SOI components: Significant progress has been made in the design of TM SOI waveguide platforms. 340nm height and 400nm width TM SOI waveguides were designed based on the rib waveguide structure and using a 50nm slab region, exploiting an 800nm SOG coating. Propagation losses of this layout were finally measured to be 1.5dB/cm. TM grating couplers with more than 50nm bandwidth at the 1550nm spectral band were designed, which were predicting a theoretically calculated insertion loss of 3.25dB/coupler and were finally measured to have 3.2 dB/coupler.

Electronic Circuitry: The IC circuits required for header detection and control signal generation in the 2×2 and 4×4 router platforms have been designed and their performance has been tested both in simulations as well as in FPGA-board deployments. Successful header detection in RTL and gate-level simulations have been carried out.


Design of plasmonic switching elements

All necessary specifications for the 2×2 plasmonic thermo-optic switches were defined within this task and a range of detailed designs for a variety of plasmonic thermo-optic switching architectures both with PMMA and with Cyclomer loadings have been produced. The switching architecture for state-of-the-art DLSPP configurations using PMMA polymer loading was at first level optimized prior proceeding with the numerical analysis and design with Cyclomer loading towards the optimization of performance when the high thermo-optic coefficient (TOC) polymer is used.

A range of different plasmonic switching structures has been designed and numerically investigated for PMMA loading that has a TOC of -1×10-4. These structures have been:

  • An all-plasmonic 2×2 Mach-Zehnder Interferometric switch
  • A hybrid Si-DLSPP 2×2 Mach-Zehnder Interferometer using Si-based 3dB couplers and PMMA-based DLSPP waveguides only at the two MZI branches.
  • An All-Pass DLSPP Waveguide Ring Resonator (WRR) that can be used as an ON/OFF switch
  • An Add/Drop DLSPP Waveguide Ring Resonator (WRR) utilizing different waveguide gaps at the Add and Drop input ports, optimized for 1×2 switching operation.
  • An Add/Drop DLSPP Waveguide Ring Resonator (WRR) utilizing the same waveguide gaps at the Add and Drop input ports, being in this way suitable for 2×2 switching operation.
  • An All-Pass DLSPP Racetrack Resonator.
  • An Add/Drop DLSPP Racetrack
  • A 2×2 DLSPP Directional Coupler switch (DCS)
  • A 2×2 DLSPP MMI Coupler switch
  • A 2×2 DLSPP Desynchronized Coupler (DSC) switch
  • An All-Pass DLSPP Microdisk switch
  • A 2×2 DLSPP Asymmetric MZI switch (A-MZI) that employed two equal length DLSPP MZI arms, but provided a pi/2 phase difference between the two propagating signals by means of a small section of wider PMMA loading. This layout leaded to high extinction ratio values requiring a phase variation of only pi/2 instead of pi needed in the conventional MZI, allowing in this way for low-loss plasmonic switching within the propagation length of PMMA-loaded SPP waveguides despite its rather low TOC value.
  • A 2×2 DLSPP dual-WRR switch that incorporated two ring structures coupled to two 90o crossing waveguides. This type of switch significantly increased the extinction ratio performance at the two output ports compared to the single-ring switching elements even when using the low TOC PMMA loading, increasing at the same time the 3-dB bandwidth of the resonance peaks and facilitating operation with WDM data packet traffic.

A new type of Long-Range DLSPP waveguides has been theoretically investigated and subsequently designed in detail. This waveguide layout enables increased SPP propagation distances up to a few millimeters allowing for enhanced thermo-optically induced phase effects even when using PMMA loadings, however it required a different material structure with two material layers below the gold film.

Cyclomer has been finally decided to be the high TOC polymer of choice. The same set of plasmonic switching structures investigated for PMMA loadings has been also designed for Cyclomer-loading, whose TOC value has been measured to be -2.95×10-4 K-1 at 250nm processing, i.e. almost three times higher than PMMA’s respective coefficient.

The numerical analysis for Cyclomer-loaded plasmonic switches revealed that the 2×2 dual-WRR, the Si-plasmonic MZI and the A-MZI switch design can offer the expected performance for PLATON’s routing platforms. MMI switches can also in principle provide high-quality switching, having however increased sensitivity to fabrication inaccuracies.

Figure 1-3: Snapshot of the PMMA-loaded SPP switch designs.
Figure 1-3: Snapshot of the PMMA-loaded SPP switch designs.
Figure 1-4: Snapshot of the Cyclomer-loaded SPP switch designs.
Figure 1-4: Snapshot of the Cyclomer-loaded SPP switch designs.

Development and system-level routing performance analysis of first interconnected test structures

The first proof of the data capture of PMMA-loaded SPP structures integrated on a SOI waveguide platform has been demonstrated with the following experiments:

  • Single Channel Transmission: The transmission performance of a 60μm-long straight PMMA- ‐loaded SPP waveguide that was hosted in a Si-plasmonic chip was initially assessed in a 10Gb/s 27-1 NRZ transmission experiment. The successful 10Gb/s data transmission over the 60μm-long plasmonic waveguide was verified by Bit Error Rate (BER) measurements, exhibiting error-free operation with negligible power penalties (<0.2dB) compared to the B2B performance.
  • OTDM Signal Transmission: The transmission performance of the 60μm-long straight plasmonic waveguide was evaluated at 160Gb/s serial data rates by using the OTDM technique for multiplexing sixteen 10Gb/s 27-1 RZ signals. Error-free operation was verified for all sixteen 10Gb/s channels that were well-confined within 1dB receiver’s powerrange and exhibited power penalty values ranging from 0 to 0.5 dB against the B2B measurements. Therefore, the signal’s propagation through the DLSPP section was performed without degradation on time and frequency domains demonstrating the efficiency of plasmonics for the transmission of signals that occupy very large bandwidth.
  • WDM Signal Transmission: The transmission performance of the straight PMMA-based waveguide was also evaluated in even higher data rates by multiplexing 12 channels based on the WDM technique for a total throughput of 480Gb/s, considering 200GHz channel spacing and 40Gb/s 231-1 NRZ line‐ Error-free operation with 10-12 BER values was obtained for six out of the twelve channels, with their power penalty ranging between 0.2 and 1 dB against the B2B measurements. The remaining six channels exhibited an error-floor at 10-7 due to their spectral position, since their wavelengths were not located within the flat spectral band of the TM grating couplers experiencing in this way higher losses. Even so, this experiment has validated for the first time the WDM data carrying and signal integrity credentials of DLSPP waveguides.

This task has also demonstrated experimentally a novel power monitoring concept for optical signals at telecom wavelengths with a responsivity of 1.8 μV/μW at λ = 1525 nm for 1V bias voltage.



  • 2×2 and 4×4 silicon-plasmonic router architectures and respective designs
  • Significant impovements in low-loss TM SOI waveguide platform and grating coupler designs
  • A great range of DLSPP plasmonic switch designs, both with PMMA and Cyclomer loadings
  • Data carrying and signal integrity credentials of DLSPP waveguides through single-channel and WDM channel transmission experiments, up to 0.48Tb/s

WP3 – SOI platform and RF/IC circuitry development

Workpackage objectives

This workpackage dealt with the development and fabrication of the SOI optical board, where the active and passive devices were mounted and assembled. The main objectives were:

  • Fabrication and testing of silicon to DLSPP interfaces
  • Development of SOI photonic circuitry
  • Hybrid integration of low-rate photodiodes on SOI motherboard
  • Design and Development of RF circuitry
  • Design and Development of logic ICs


Progress towards objectives detailed for each task

Fabrication and testing of silicon to plasmonic interfaces

Si-to-DLSPP interfacing structures have been designed and developed based on a butt-coupling approach. Several structures relying on the Si-rib waveguide platform were deployed and characterized, revealing an average insertion loss of 2.5dB when a gap of 500nm is exploited between the SOI and the DLSPP waveguide. Theoretical analysis showed that this value can go down to 1dB if no gap is used between the SOI and the DLSPP waveguide.


Fabrication and characterization of logic ICs

A prototype of the ASIC to be employed in the PLATON Router has been fabricated (Fig. 1-5) by AMS using 0.35um CMOS technology and was then evaluated. The process featured four metal layers for interconnects, two polysilicon layers for gate electrodes and interconnects, high resistivity polysilicon structures and output buffers with output voltage up to 3.3V and current of 24mA.

Figure 1-5: Photography of control IC (Left), Packaged control IC for testing (Right)
Figure 1-5: Photography of control IC (Left), Packaged control IC for testing (Right)

The results of the bit pattern measurements are shown in Figure 1-6. The plots show the output patterns (rows 4-11) for three different input bit patterns (rows 2 and 3). For all bit pattern it can be seen that the outputs change 1 μsec after the inputs have changed.

Figure 1-6: Bit-pattern measurements of PLATON ASIC
Figure 1-6: Bit-pattern measurements of PLATON ASIC

Fabrication and characterization of SOI  platform photonic circuitry and monolithic integration of low-rate photodiodes

The fabrication of the SOI motherboard for the 2×2 router platform has been successfully realized by using a so-called Mix&Match technology, which is a combination of electron beam lithography and photolithography on 6’’ SOI wafers, making use of the specific advantages of the two lithography methods. Following this process, a number of router chip SOI motherboards have been successfully implemented, hosting the following on-chip functional blocks:

  • A TM SOI platform with significant improvements compared to the TM SOI components fabricated during the first two project years. The propagation losses were reduced down to 1.5dB/cm and TM grating couplers with insertion losses lower than 4dB/coupler were fabricated, leading to an overall loss reduction of approximately 20dB compared to the first respective configurations implemented during the first project year.
  • Two 8:1 SOI-MUX configurations, which were successfully evaluated with respect to their optical performance, showing 32 SOI microring resonators operating simultaneously on the same chip.
  • A gold lift-off area that was subsequently successfully exploited for the deposition of the plasmonic switches.
  • Metal heaters for tuning the SOI-MUX ring resonators, RF and DC metal interconnects for guiding the RF and DC electrical signals.

In the following Figure 1-7 the layout of the SOI motherboard realized in this task is shown. The plasmonic switches, SOI multiplexers and process control structures are highlighted.

By employing AMO’s Mix&Match technology and the specially developed process, multiple chips with the layout have been fabricated on 6’’ wafers. Figure 1-8 shows a picture of a final 6’’ wafer with a total of 12 chips and an overview picture of one chip.

Figure 1-7: Overview Layout Plasmonic Router: Plasmonic switches, SOI multiplexers including thermally tuneable microrings and process control structures are highlighted
Figure 1-7: Overview Layout Plasmonic Router: Plasmonic switches, SOI multiplexers including thermally tuneable microrings and process control structures are highlighted
Figure 1-8: Picture and microscope image of the final wafer and chip showing the decoration of the wafer with a total of 12 dies (nanophotonic structures may only be present on several chips) and the final structures on the chip.
Figure 1-8: Picture and microscope image of the final wafer and chip showing the decoration of the wafer with a total of 12 dies (nanophotonic structures may only be present on several chips) and the final structures on the chip.

Monolithic all-silicon photodiodes were successfully implemented and characterized. Defect states inside silicon were generated by means of Si+-ion implantation as a way to drastically increase the linear absorption. The active length of the investigated detector structure was LPD=1.0 mm and an ion implantation dose of 1e13cm² at an acceleration voltage of U=130keV has been used, masked with an implantation window defined by electron beam lithography centered to the silicon waveguide. Static electro-optical characterization results were obtained revealing a linear characteristic behavior between generated photocurrent versus injected optical power with a sensitivity of 0.1 A/W. Dynamic characterization was also carried out, showing that the photodiode is able to detect modulated optical signals up to 1MHz, which is sufficient for PLATON router’s header detection purposes where header signals with 1μsec duration are targeted.


Fabrication and characterization of SOI RF circuitry

Several metallization layers have been successfully fabricated into the SOI and DLSPP chips that control the microrings and the switches, respectively. The whole process has been applied to several chips that were developed within PLATON with repeatable results, indicating that this has been established now as a routine process for AMO, SDU and UB. The performance of the RF lines on the Si substrate in the sub MHz range, where the electrical signals of the router operated, was also evaluated revealing quite low propagation losses (2.5dB/cm) and frequency independent behavior, suggesting that there is no need for pre-emphasis of the signals.

Significant results

  • The Si-to-DLSPP coupling structures with 2.5 dB insertion losses that can be optimized towards being reduced to 1dB.
  • The success in the complex structure of the SOI motherboard for the 2×2 PLATON router, with 32 microring shown to operate successfully on the same chip.

WP4 – Development and System-Evaluation of Plasmonic Switching Elements

Workpackage objectives

  • To develop the three different thermo‐optic 2×2 DLSPP switch configurations in a fiber‐pigtailed form(using the three implementations proposed in WP2: DC/MZI/WRR)
  • To characterize the thermo‐optic 2×2 switch in CW mode via Scanning Near‐Field Optical

Microscopy (SNOM) and in system‐level experimental testbed at 10 and 40Gb/s.

  • To develop in a single fabrication step a 4×4 DLSPP‐based switching matrix and evaluate its performance both in CW and in dynamic, system‐level experimental environment
  • To develop and evaluate an all‐optical single element photonic switch


Progress towards objectives detailed for each task


Fabrication, characterization and system-level evaluation of single element 2×2 thermo-optic plasmonic switch

The following DLSPP switching structures have been fabricated and experimentally demonstrated: a) Mach-Zehnder Interferometer (MZI) and b) Multi-Mode Interferometer (MMI)

  1. PMMA-loaded A-MZI with 90μm long DLSPPs: An asymmetric MZI switch architecture initially biased at a π/2 phase bias was deployed and the first system-level experimental results were obtained for this structure under static and dynamic control conditions, using a CW as well as true 10Gb/s NRZ 27-1 and 231-1 PRBS data signals. Successful switching operation has been obtained, revealing ER values of 6dB and 1dB for the CROSS and BAR MZI ports, respectively, when driving the A-MZI with 30mA electric current. The poor performance of the BAR port owes to the use of 95:5 instead of 3-dB directional couplers at the A-MZI, originating from an unfortunate design error in the first structures. The rise and fall times of the switched output signals were also measured for the first time, and were found to be lower than 3μsec and 5μsec, respectively, while the power consumption requirements were lower than 11mW. BER measurements demonstrated successful transmission during both ON and OFF switching states of the A-MZI with up to 1.7dB power penalty (at 10-9 BER value) compared to the B2B measurements. This activity had two important scientific impacts: a) it has confirmed for the first time the fast (μsec-scale) thermo-optic response and the low power (mW-scale) consumption of the DLSPP switches, b) it has highlighted DLSPPWs as the best thermo-optic switch technology with respect to power-time response product metric, rendering DLSPPs as the most efficient TO switch technology towards offering low energy and fast response simultaneously.
  2. PMMA-loaded A-MZI with 60μm long DLSPPs: Experimental proof of low-energy switching functionality in true data traffic conditions has been also attained for a 60-μm-long PMMA-based A-MZI under single-channel and 4-channel (WDM) operation with total aggregate capacity of 40Gb/s (4x10Gb/s, PRBS 231‐1 encoded). In single-channel operation, ERs of 14dB for the CROSS port and 0.9dB for the BAR port have been attained when employing 10Gb/s NRZ 231-1 PRBS data signals and 40mA driving electric current for the control signal. The poor performance of the BAR port stems again from the use of 95:5 silicon directional couplers. The rise (on) and fall (off) times of the switched signals were found to be 3.8μs and 2.3μs, respectively, and the switching power consumption for pi/2 phase shift was 13.1mW. The signal integrity in transmission under the presence of the Si-plasmonic switching element was verified by the error-free performance with negligible power penalties (up to 0.15dB) that was achieved for the ON state and 1.7-3.6dB for the OFF state. Taking into account the broadband characteristics of the MZI layout as well as the WDM-enabling transmission capabilities of DLSPP waveguides up to at least 480Gb/s aggregate data rates (see T2.4), these results indicate that switching of a 480Gb/s multi-wavelength packet stream with lower than 0.03 mW/Gb/s power consumption values should be feasible.
  3. PMMA-loaded MMI: A PMMA loaded 2×2 MMI switch was evaluated with a single channel 10Gb/s 231-1 single channel signal. The MMI had 75μm interaction length and the applied control pulses were 2.3Vpp/50mA with 30% duty cycle. Under these conditions the ER of the switch were calculated 4.2dB and 1.2dB in CROSS and BAR states, respectively. The performance of the CROSS port was superior to BAR port due to a design issue related to the different losses experienced by the symmetric and the antisymmetric modes of the MMI. The 10-to-90% rise and fall times of the switch were measured to be 2.9μs and 4μs, respectively. The power penalty in the BER measurements was found to be less than 0.3dB in line with the results obtained from the PMMA loaded MZIs. Switching with MMIs is an alternative approach that is very useful for Network-on-Chips due to their lower footprint and simple driving scheme compared to A‐
  4. Cyclomer-loaded MMI: The first thermo-optic switching experimental results with Cyclomer-loaded MMIs have been demonstrated, using a 119μm-long and 800nm-wide MMI design in order to ensure that only two guided modes are supported in both cool and hot states. For 400mA DC current injection through the gold film that induced a temperature variation of ΔΤ=60Κ, successful 2×2 thermo-optically induced switching operation was achieved yielding an ER of ~7dB at 1566nm wavelength. The first experiment on dynamic switching with Cyclomer-based long MMI structures was initially performed at 0.5Hz, with 320mA current applied to the gold film, revealing 5dB and 2dB ER values for the upper and lower ports, respectively.


Fabrication, characterization and system-level evaluation of single element 2×2 thermo-optic waveguide-ring resonator plasmonic switch   

The following thermo-optic DLSPP WRR-based switching elements were fabricated and evaluated:

  1. All-pass thermo-optic PMMA-based racetrack switches: The first experimental results were obtained from a DLSPP WRR device relying on an all-pass PMMA-loaded racetrack structure with R=5.5μm radius, L=0.8μm interaction length and G=0.35μm gap, which was evaluated with respect to its thermo-optic response, revealing a wavelength shift of 7nm for an applied DC current of 50mA. This wavelength shift revealed an ER of 8dB at 1562nm between the COOL and HOT states of the device, corresponding to an induced temperature change of 61K and consuming only 3.3mW of electrical power.
  2. 2×2 Cyclomer-based WRRs: Experimental characterization regarding thermo-optic tuning of a 2×2 switch showed clear resonant peaks spaced apart around 34nm and 15dB extinction ratio. Thermo-optic response for a WRR was measured on a structure with a ring radius of 6 um, a gap of 0.4 um and an interaction length of 1.5 um, and a maximum shift of 8 nm was observed for 80 mA of current through the WRR.
  3. 2×2 Cyclomer-based dual- racetrack resonator (X-Add/Drop) switches: A Cyclomer-loaded dual-racetrack resonator switch has been fabricated using 250nm deep UV lithography and the first thermo-optic response characterization results have been obtained. The DLSPP racetrack resonators were placed in a non-symmetric orientation and had R=5μm radius and two straight waveguide region lengths of L1=2μm and L2=0μm respectively. Besides, a gap resolution of 300nm was achieved between the intersecting waveguides and the racetrack resonators. The FSR of the WRRs was found to be 38nm. When operating in unheated conditions, the resonant dips at the Through-port revealed more than 35dB ER, while the corresponding ER value for the Drop-port resonant peak was close to 10dB in the 1560-1580nm spectral region. Driving the switch with 400mA DC current a wavelength shift of 9nm was observed at both through and Drop-port resonances. ER values higher than 6dB were obtained over a 6nm spectral range around 1558nm for both output ports confirming the improved switching credentials of the Cyclomer-loaded compared to the PMMA-loaded SPP platform. This was the first experiment with X-Add/Drop switch and confirmed the superior performance of this design compared to the simple WRRs.

Fabrication, characterization and system-level evaluation of a 4×4 thermooptic DL-SPP-based switching matrix

A 4×4 thermo-optic DLSPP switching device has been tested with fast prototyping process, relying on four X-add-drop structures linked together in a 4×4 blocking switch arrangement. Light propagation in this 4×4 switching device has been observed by leakage radiation microscopy. However, due to a) a defect at the crossing area of the two waveguides originating from a local over exposure and b) the high total losses of the cascaded X-add- drop structures (more than 20dB in total), device operation could not be characterized by extracting transmission spectra for each output port. However, the 4×4 system was investigated for its correct operation by employing two different wavelengths spaced by ~25nm, revealing clear switching of direction between the two directions.

Both normal and asymmetric MZI based 4×4 switching matrices were implemented on SOI chips with integrated Si waveguides, by UV lithography and Au lift-off processing. The quality of both the Au and the Cyclomer level components was superior in terms of LER and resolution, with respect to previous chips, because of a bi-layer resist process that was applied for the gold level fabrication and the optimization of the UV dose factor for the Cyclomer level lithography. The resulting switching elements were characterized structurally by SEM and AFM and their characteristics were found to be consistent to the nominal ones. However, the attempts for complete characterization of the chips were prevented by the huge insertion losses arising by the TM grating couplers, the several Si-to-DLSPP coupling sections and the switches itself. The insertion losses imposed by the chip were >60dB imposing an insuperable barrier for the characterization of the switching matrices. Moreover, Cyclomer 4×4 thermally controlled switches relying on dual-racetrack resonators were fabricated by EBL and characterized by Leakage Radiation Microscopy. The 4×4 thermo-optic DLSPP switching device was tested with the fast prototyping process. The switching of direction between the two ports was demonstrated by performing a sweep at a wavelength range of 25nm, but again the insertion losses were very high.

The effort on 4×4 switching matrices stopped after deciding to devote more resources to the 2×2 router prototype activities in order to obtain at least one successful prototype device. Within this frame, this task shifted its resources and its focus towards optimizing the Cyclomer-loaded SPP waveguide fabrication process as a means to improve measurement repeatability and stability with the final aim being its application to the 2×2 DLSPP-on-SOI switching elements. Indeed, this resulted to an optimized Cyclomer process where hardbaking was applied before applying plasmonic deposition on the SOI platform, significantly improving experimental measurement repeatability and stability with respective results being summarized in WP6.

Fabrication and characterization of an 1×2 all-optical plasmonic switch  

An optically-controlled photo-thermally activated dielectric loaded plasmonic switch comprised of gold nanoparticle-doped polymer deposited onto a gold film has been fabricated and demonstrated. These switches rely on a multi-mode interferometer design and are fabricated by electron beam lithography applied to a positive resin doped with gold nanoparticles at a volume ratio of 0.52%. A cross-bar switching is obtained at telecom wavelengths by pumping the devices with a visible beam having a frequency within the localized surface plasmon resonance band of the embedded nanoparticles.

By comparing the switching performances of doped and undoped devices, the modest doping levels applied in this case lead to power consumption reduced by a factor 2.5 compared to undoped devices. The minimization of activation power is attributed to enhanced light-heat conversion and optimized spatial heat generation for doped devices and not to a change of the thermo-optic coefficient of the doped polymer.

A summary of the achievements made with reference to the planned objectives:

  • Investigation of photo-thermal activation of 1×2 dielectric loaded plasmonic switches
  • The switches which rely on a MMI design were fabricated by electron beam lithography using a NP-doped positive resin
  • Spectral response of 140 µm-long MMI waveguides at room temperature revealed a switching between the CROSS and the BAR state with typical extinction ratios around 20dB over a wavelength range of 30±5nm for both doped and undoped devices.
  • For the purpose of comparing the power needed to thermally activate doped and undoped switches, the thickness of polymer leading to an optimum light-heat conversion when illuminated at 532 nm has been determined by analyzing absorbance spectra of homogeneous layers.
  • For an optimized thickness of 400 nm, the light-heat conversion efficiency at 532 nm is enhanced by a factor 2 by the presence of the NPs.
  • The polymer material has been engineered to enhance light-heat conversion


Significant results

  • Successful integration of several DLSPP switch architectures on the SOI platform, turning this into a routine process.
  • A novel Asymmetric MZI DLSPP switch design for reducing the necessary phase shift and allowing for lower footprint, lower loss and lower energy DLSPP switches.
  • The system-scale evaluation of DLSPP switches on SOI, revealing for the first time the μsec time response characteristics and the mW-scale power requirements.
  • The WDM data switching capabilities of DLSPP switches
  • The demonstration of the lowest Pxτ value among all thermo-optic switch technologies, confirming for the first time the energetic efficiency of plasmonics.
  • The photo-thermal all-optical switch that can lead to sub-μsec switching times.

WP5 – Development and System-Evaluation of Plasmonic Switching elements

Workpackage objectives

WP5 was assigned to the integration of the 4×4 and 2×2 plasmonic switching elements on SOI motherboard, to the hybrid integration of the IC microcontroller circuit and to the packaging and fiber-pigtailing of the final 2×2 and 4×4 routing platform prototypes. Its main objectives were:

  • to integrate plasmonic switching elements on the SOI motherboard platform
  • to hybridly integrate the RF interconnections and the IC circuitry on the SOI motherboard
  • to produce the final, packaged and fiber-pigtailed PLATON’s 2×2 Tb/s optical routing platform for optical  interconnects applications
  • to produce the final, packaged and fiber-pigtailed PLATON’s 4×4 Tb/s optical routing platform for optical interconnects applications
  • to deploy a coherent design methodology and design flow towards a 3D System-in-Package (SiP) integration of silicon photonics and plasmonics

Progress towards objectives detailed for each task

Deposition of the 2×2 plasmonic switching elements on SOI motherboard

To address the challenge of integrating the plasmonic part in the relatively deep cavity on the SOI motherboard, a novel type of photomask for optical photolithography has been introduced. With this specifically recess etched “2.5D photomask”, the topography of the mask was matched with the one of the chip. This was necessary to keep the intimate contact between the Cr mask and the resist absolutely needed to achieve the 500nm resolution required for the polymer waveguides. This 2.5D photomask technique was used only for the cyclomer step because the gold level requirements were not as strict as the polymer one.

For the gold level fabrication, a bi-layer photoresist lithography process was applied followed by thermal metal evaporation and subsequent lift-off. The lithography mask used was the standard one as it does not need to be a recess mask in that case. The following Figure displays the resulting Au electrodes of the MZI switch.

Figure 1-9: SEM micrograph of the MZI switch after the gold level fabrication.
Figure 1-9: SEM micrograph of the MZI switch after the gold level fabrication.

Following the gold level definition, the cyclomer was applied by using the specially designed recessed 2.5D photomask for UV exposure. The overall integration of the plasmonic part showed variation between the nominal and the actual values of less than 5% where the achieved alignment accuracy were better than the machine’s specs of 0.25µm. Taking into account the difficulty of the processing and the introduction of the novel 2.5D mask processing, the plasmonics integration into the router chips must be considered as a major accomplishment within this task.

Integration of RF and IC circuitry in the 2×2 routing platform

Several DC electrical I/Os were required in the 2×2 router prototype in order to bias the double ring resonator structures of the 1×8 MUX as well as the DLSPP A-MZI switch. The following figure shows the entire layout of the 2×2 PLATON router with its MUX and 2×2 switching matrix including the electrical signal paths.

Figure 1-10 GDS layout of the 2x2 PLATON router
Figure 1-10 GDS layout of the 2x2 PLATON router

A major challenge has been to bring the required plasmonic switch and SOI-MUX contacts over the entire chip to the borders of the entire 2×2 router in order to contact them using wire bonding schemes to the periphery of the router. That enabled to control each of the required component separately, namely the 2nd order ring resonators and the DLSPP based switching elements (figure 1-11).

Figure 1-11 Challenge of heteronomous integration, compatibility issues related to AU and Al
Figure 1-11 Challenge of heteronomous integration, compatibility issues related to AU and Al

Due to the process complexity, a straight forward solution of separately processing the Al signal paths on silicon integration platform has been chosen and then further interfacing the DLSPP switching elements using wire bonding.

Figure 1-12 Wire bonding approach to overcome the challenge
Figure 1-12 Wire bonding approach to overcome the challenge

Figure 1-12 indicates also the process flow to be considered in order to get the DLSPP switching elements to be contacted: after finalizing the silicon photonics integration platform processing with the required cavity for the DLSPP elements, the plasmonics components got fabricated, they were then contacted to the Al contact pads, which have been already processed within the silicon platform. The two different heights on the substrate were interconnected using wirebonding.

Further interfaces to be considered were related to the ASIC integration on the router platform. All have been considered in the figure 1-13.

Figure 1-13 PLATON 2x2 silicon photonics and ASIC integration layout
Figure 1-13 PLATON 2x2 silicon photonics and ASIC integration layout

These processes for the RF and DC electrical line integration were successfully applied in the 2×2 PLATON router prototype chips.


Packaging and fiber pig-tailing of the 2×2 routing platform

Figure 1-14 shows the 2cmx2cm PLATON 2×2 router chip with corresponding ASIC chip to be hybridly integrated on the silicon photonics platform and interfaced both optically and electrically. Although the dimensions of the silicon photonics 2×2 router chip are small since a dense integration is possible due to the silicon photonics nanowire concepts, the interfaces to the periphery defines the dimensions of the package. Here standard multi fiber arrays and standard electrical pin arrays were implemented to the router, which were defined in sub millimeters and millimeters.  Due to the wire bonding considerations and boundaries, the landing pads for wire bonds have been selected to be pad sizes dimensioned 100µmx100µm with a pitch of 50µm.

A photograph of the completely packaged 2×2 PLATON router prototype prior the fiber-pigtailing is shown in Fig. 1-15. A total number of 79 electrical connections and 22 optical I/Os were finally incorporated.

Figure 1-14 Detailed plan of PLATON 2x2 router package integration
Figure 1-14 Detailed plan of PLATON 2x2 router package integration
Figure 1-15 The completely packaged 2x2 PLATON router
Figure 1-15 The completely packaged 2x2 PLATON router

Deposition of 4×4 plasmonic switching elements on SOI motherboard

The activities described in this task were finally not carried out after deciding to drop the 4×4 router integration and proceeded instead to a second design and fabrication round of the 2×2 PLATON router. As such, the effort originally allocated for this task was redirected to the second 2×2 router run aiming at delivering a functional and successful 2×2 router prototype. To this end, the plasmonic element deposition described in this task was again concerned with the 2×2 plasmonic switch deposition, following the processes described in Task. 5.1. The 2×2 Cyclomer-loaded switches were this time integrated on seven samples of the new PLA20 chip series of the 2×2 PLATON router.

Moreover, 2×2 switch integration was carried out also in discrete SOI chips that were designed to host only A-MZI plasmonic 2×2 switches. This activity was initiated as a back-up plan to ensure at least 2×2 routing functionality by means of externally interconnected SOI-MUX and plasmonic switch chips, in case all efforts on the on-chip 2×2 router prototype would fail. Three samples were finally prepared following this layout.

Integration of RF and IC circuitry in the 4×4 switch

Due the subsequent decision about refocusing on optimized 2×2 PLATON router instead of proceeding to the 4×4 prototype, the efforts allocated originally in this task were devoted to the respective activities for the PLA20 chip series of the 2×2 router, extending and applying again the concepts and techniques identified in Task 5.2.

Packaging and fiber pig-tailing of the 4×4 switch

Three samples obtained by the second fabrication run of the 2×2 router prototype (PLA20 chip series) were successfully packaged and pigtailed in this Task. The following figure shows an image of the wire-bonded 2×2 router chip. The final packaged chip was housed in a housing module being similar to the one used for the PLA19 2×2 router packaging.

Figure 1-16 Wire bond connections of PLATON router chip
Figure 1-16 Wire bond connections of PLATON router chip

3-D Integration perspective of silicon and plasmonic platform

A CMOS-compatible concept for the underlying technology to enable next generation optical computing architectures has been identified. By introducing a new optical layer within the 3D SiP, the development of converged microsystems, deployment for next generation optical computing architecture will be leveraged. Technologies such as 3D integration and wafer level packaging are leveraging the functionalities of MEMS components. PLATON 3D SiP has the potential to overcome the key bottleneck to the realization of high-performance microelectronic systems and leverage low-latency and high-bandwidth communication in converging technologies, where frontiers are disappearing. By using such a high bandwidth photonic interconnection layer, IZM has addressed the vision of optical computing within next generation architectures.


Significant results

  • 2.5D integration of plasmonics onto the SOI motherboard
  • Packaging and fiber-pigtailing of the 2×2 silicon-plasmonic router
  • the successful fabrication of Cyclomer-loaded switches

WP6 – Experimental evaluation of the 2×2 and 4×4 Tb/s routing platform

Workpackage objectives

  • To implement a WDM 40Gb/s optical test bed simulating data traffic used in short-range data communications
  • To evaluate the performance of the packaged 2×2 Tb/s optical interconnection routing platform in a system-level experimental environment
  • To evaluate the performance of the 4×4 Tb/s optical blade interconnection routing platform in a system-level experimental environment
  • To experimentally evaluate the performance of the 1×2 all-optical DLSPP switch with Gb/s data traffic


Progress towards objectives detailed for each task


Experimental performance evaluation of the packaged 2×2 optical interconnection routing platform

A WDM 40Gb/s optical test bed simulating data traffic used in short-range data communications was implemented.

The first generation of the 2×2 PLATON router (PLA19 series of chips) was characterized revealing huge losses for all incorporated building blocks, which prohibited its utilization in system-level experiments. The second generation of optimized packaged 2×2 router modules (PLA20 series of chips) had their optical performance characterized, showing reasonable insertion losses and revealing successful optical functionality for the SOI-MUX stages. More specifically, silicon propagation losses of 3.39dB/cm and grating coupler losses of 3.68dB/coupler were obtained. Around 20dB insertion losses were measured at the through port of every 8:1 SOI-MUX structure, while the 2nd order ring resonator resonances were found to have FSR values around 7nm and 9nm corresponding to the RR designs with 12um and 9um, respectively. However, the insertion losses for the complete router device including the plasmonic A-MZI switch were again very large, in excess of 60dB.

Experimental characterization was also performed on the discrete silicon chips hosting only the plasmonic A-MZI switch (PLA22 chip series launched as a back-up plan. Successful static thermo-optic characterization was also performed, yielding to BAR and CROSS port transfer functions versus applied electrical current that confirmed the successful functionality of the 2×2 switch. Moreover, improved measurement repeatability and stability was observed with respect to the first batch of Cyclomer-loaded SPP switches, verifying the effectiveness of the hardbaking process adopted during Cyclomer waveguide processing.

Experimental performance evaluation of the packaged 4×4 optical interconnection routing platform

As the 4×4 router prototype deployment was dropped, effort allocated initially in this task was redirected to the experimental evaluation of the two generations of 2×2 PLATON routers and of the PLA22 chip series of the discrete 2×2 plasmonic switches, which were initiated as a back-up plan.

Experimental evaluation of the all-optical single element plasmonic switch

The dynamics of the thermo-modulation of PLSPPW devices photo-excited by nanosecond pulses have been investigated both experimentally and numerically. By operating a fiber-to-fiber detection scheme, we have demonstrated a response time for the thermo-absorption of the PLSPPW mode in the nanosecond regime at the scale of the pulse duration. Whatever the time scale, we have shown that the thermo-absorption of the PLSPPW mode is mediated by the temperature-dependent metal ohmic losses but also by the field distribution of the PLSPPW mode into the metal controlled by the polymer TOC. For a negative TOC, we observed a sub-μs thermo-modulation characteristic time (fall-time + rise time) about four-fold shorter than the cooling time of the metal film itself. In addition, we found that the thermo-absorption amplitude for a PLSPPW mode was about 10 times larger than for an Au/air interface SPP photo-excited in the same conditions. On the basis of these results, we concluded that the thermo-absorption effect significantly impacts the performances of the PLSPPW based TO devices. Next, we have considered the thermo-optical response of PLSPPW racetrack resonators featuring well pronounced resonances. By choosing a signal wavelength either blue or red detuned compared to the cold state resonance, we have shown that the nanosecond pulse can activate the resonator at a time scale of 300ns however followed by a characteristic cooling time of about 18μs in our configuration. The slow TO dynamics of these resonators are attributed to the poor thermal diffusivity of both the polymer and the glass substrate used in this study. In spite of these poor thermal performances, we note that the nanosecond photo-thermal excitation is convenient for sub-μs activation which is the key feature for the fast pre-conditioning of the TO devices.

Significant results

  • The photo-thermal switch activation witnsub-μsec switching times
  • The successful optical performance of the 2 8:1 MUX units on-chip
  • The high fabrication accuracy achieved with respect to identical SOI rings integrated on the same chio. AMO’s 2nd order rings showed a ring radius fabrication error lower than 5nm for both 7 and 9nm ring radii.

WP7 – Dissemination and Exploitation

Workpackage objectives

WP7 focused on the exploitation and dissemination of PLATON’s developed platform. This workpackage was responsible for the exploitation and use of the developed devices concluding a detailed business plan at the end of the project. WP7 also handled issues regarding rights on intellectual property that were expected to arise within the project’s duration and also dealt with the management of the Industrial Advisory Board that has been established. Finally, the results of the PLATON project were announced according to the specified dissemination plan. Its main objectives were:

  • Establish PLATON website.
  • Generate intellectual property (patents portfolio) to set the basis for potential commercialization of the products relevant to the project outcomes.
  • Disseminate project results through press releases, publications in scientific journals, presentations at international conferences and workshops as well as through lectures presented in academia, industry and EU policy makers.
  • Interact with other EU and national projects.
  • Provide input to industry based on technical work produced/performed in the framework of the project.
  • Produce a manufacturing plan for PLATON’s prototypes developed under the project towards cost-optimised commercial products.
  • Produce a detailed business plan, based on feasibility studies and trends to show the possibilities of both commercialisation and integration into near future commercial equipment.
  • Manage Intellectual Property Rights and ensure that IPR protection strategies will be activated before publishing
  • Monitor the newly generated knowledge world-wide in PLATON’s respective research fields.
  • Manage the Industrial Advisory Board and interact with its members.


Progress towards objectives detailed for each task


The desired target values of the Dissemination Success Indicators have been clearly overachieved. Dissemination of project foreground was performed towards the following directions:

  1. Participation and/or representation at conference booths (ECIO, OFC, ECOC, Laser World of Photonics) distributing project material and brochures
  2. Supported the establishment of the ECO interconnect, participated into its first workshop meeting co-located at ECOC 2013 inLondon.
  3. Co-organized symposia and workshops at OFC2012, ECOC2012 and ECOC2013
  4. Web-Site ( ):
    1. Statistics: ~8000 worldwide visits.
      1. Keeps updated (News, list of publications, IAB members and deliverables in public and private areas) and fixed/corrected/enhanced for improved Google search hit results.
    2. Numerous publications:
      1. Journals/White papers/Magazines: 27 (2 invited)
      2. Book Chapters: 2, both after invitation
      3. Articles in Magazines: 3
      4. Conferences/Seminars/Workshops: 57 (35 invited).


Exploitation and use

Academic Exploitation: The number of PhD students that have completed or are close to their completion of their PhD degree in thematic areas relevant to PLATON concepts and technologies has been 9 in total (Mr. O. Tsilipakos, Mr. A. Pitilakis, Ms. A. Tasolamprou, Mr. S. Papaioannou, Mr. K. Hassan, Kr. J. Gosciniak, Mr. A. Prinzen, Mr. D. Kalavrouziotis, Mr. G. Giannoulis). Updated material on PLATON’s technical content has been incorporated in under- and postgraduate lectures at the Aristotle University of Thessaloniki (affiliated with CERTH), at ICCS/NTUA, SDU, UB and Technical University Berlin (affiliated with IZM).

Research Exploitation: Customized simulation tools for plasmonic and silicon components have been established as well as a novel platform that interconnects component and system level simulation tools for reliably addressing the system-level performance of complex structures relying on plasmonics and silicon photonics. Based on the final experimental test-bed that had to be deployed within WP6 of PLATON, CERTH and ICCS/NTUA have initiated efforts to expand this testbed and produce the first European optical interconnect testbed that will be capable of evaluating a great range of optical chips and boards in true multi-processor, HPC and Data Center traffic conditions.

New project ideas and new funding exploitation: New ideas that have been developed within PLATON consortium have been exploited for the successful submission of the IP project PhoxTrot ( on “Optical Interconnects” to the FP7 ICT Call 8. All PLATON partners are members of this new consortium and have been the main initiators.

European Optical (ECO) Interconnect cluster establishment: PLATON has strongly supported this initiative that has been formed within the frame of the PhoxTrot project

IPR management

UB has successfully filed throughout the duration of the project the two following patents:

  • “Composants thermo-électriques plasmoniques intégrant un système de mesure de la puissance guide” (application reference: F-11 67490, applicants: J.-C. Weeber, A. Dereux from UB)
  • “Procédé de fabrication d’un masque de lithographie UV par contact et de puces optoélectroniques au moyen d’un tel masque” (application reference: F-13 55540, applicants: L. Markey, F. Zacharatos from UB)

Industrial Advisory Board management

The IAB has been established and efforts towards expanding the number of its participating companies were continuously carried out until the end of the 2nd project period. The IAB comprised the following industrial members: IBM Zurich (Switzerland), Luxdyne (Finland), Oclaro (UK), Constelex Technology Enablers (Greece) and Alcatel-Lucent (Germany). An NDA has been produced by CERTH and after agreed between all PLATON partners has been signed by all partners (Luxdyne, Oclaro, Constellex, ALU), except IBM.

Significant results

  • A high number of high-quality publications and invited articles.
  • The organization of the first workshops at the OFC and ECOC conferences, which were a milestone in the effort to bring the optical communications and the plasmonics communities closer towards accelerating practical applications of plasmonics. This can be confirmed also by the fact that an additional symposium was organized during ECOC 2013, without the active participation of PLATON members in its organization, suggesting that indeed the first two workshops organized by PLATON members were very well perceived by the optical communications community.
  • The 2 patents filed.
  • The general impression received all PLATON members during conferences/workshops that PLATON has been a pioneering project in the area of plamonics and has discouraged all other plasmonics groups from competition. The common conclusion from several well-known groups in the US was that Europe seems to be ahead in the field of plasmonic interconnects.


PLATON tackled the problem of cable size and energy consumption in Data Centers and High-Performance Computing Systems (HPCS). Its router prototype technology intended to exploit plasmonics as low-energy, small-size and high-bandwidth switches overcoming their propagation loss limitations through merging plasmonics with a low-loss silicon photonics platform. To this end, PLATON turned plasmonics from a fascinating research field into an established and “practical” key enabling technology. This opened completely new perspectives for the employment of plasmonics in several application fields, enabling the utilization of all their beneficial aspects, namely footprint and energy consumption. This opened up the possibility for new, advanced plasmonic components and at the same time created real opportunities for their commercial uptake by cracking their critical problems associated with propagation losses. PLATON intended to demonstrate this roadmap by confirming the incorporation of “practical” plasmonics into chip-scale Tb/s router prototypes, reducing the power consumption by more than three orders of magnitude compared to state-of-the-art electronic routers in Data Center environments. Together with the silicon-plasmonic blending that can yield common fabrication processes and lower the fabrication cost, the energy and size advantages of PLATON’s router technology bear the promise of a groundbreaking interconnect technology with significant potential for penetrating the commercial sector of optical interconnects and Data Centers.

The PLATON Consortium