POLYSYS

Direct 100G connectivity with optoelectronic POLYmer-InP integration for data center Systems

[October 2010 – January 2014]

Project Overview

POLYSYS aimed to realize for the first time serial 100 Gb/s direct connectivity in rack-to-rack and chip-to-chip data communications systems. In specific, POLYSYS focused on the development of photonic and electronic components operating directly at 100 Gb/s based on electro-optic polymers enabling the best possible material compatibility with current polymer-based optical backplanes. The technical objectives of POLYSYS were achieved through the cost-effective polymer material system for realizing the electro-optic components and the utilization of InP for developing high-performance optical and optoelectronic components.

After 40 months of development efforts it can be said that POLYSYS has been extremely successful in helping EO polymers evolve from a device specific technology into a broader purpose platform for small-scale and high-performance integrated circuits for datacom applications. Achievements to this direction include:

  • The monolithic integration of MMI couplers and tunable Bragg-gratings together with MZMs on EO polymer chips.
  • The hybrid integration of InP chips (laser diodes, gain chips, photodiodes) with EO polymer chips and the development of lasers with 17 nm tunability combining InP gain chips with monolithic Bragg-gratings.
  • The integration of EO polymer chips with InP-DHBT circuits using wire-bonds and the packaging of integrated transmitter modules.

At the same time, POLYSYS has also been extremely successful in extending the limits of InP photodetector technology and developing quad arrays of pin-photodiodes and pinTWAs with potential for 100G operation, as well as in advancing the state-of-the-art of InP-DHBT technology and developing novel MUX-DRV circuits and twin-DEMUX circuits for operation at 100 Gb/s. Through the integration of all these components, POLYSYS has impressively achieved the final packaging of six out of the seven modules that had targeted:

  • The 100 Gb/s transmitter
  • The 2×100 Gb/s transmitter
  • The tunable 100 Gb/s transmitter
  • The 100 Gb/s integrated optical interconnect
  • The 4×100 Gb/s pin-DEMUX receiver
  • The 4×100 Gb/s pinTWA-DEMUX receiver

Four of these modules (100G Tx, 2x100G Tx, tunable 100G Tx and 4x100G pin-DEMUX receiver) were successfully tested and confirmed the potential for error-free operation at 80 and 100 Gb/s and transmission over SMF links of at least 1km without dispersion compensation, whereas the testing of a fifth one (4x100G pinTWA-DEMUX) will be completed after the final review meeting.

POLYSYS gained remarkable visibility through a variety of dissemination actions and prestigious publications (including the ECOC 2012 PDP), and succeeded in defining concrete exploitation plans by all partners. Significant achievements that are related to the actual exploitation of the foreground knowledge are the industrial strategic partnership between GigOptix and HHI in the last period of the project and the funding of a follow-up research project (http://www.ict-panther.eu/) that was based on the knowhow of POLYSYS.

 

Summary of project context and objectives

New broadband applications continue to emerge, increasing the required bandwidth in every part of the network. The amount of information that is exchanged today is creating real pressures in modern data-centers. The incorporation of thousands of servers has created the necessity to transfer massive amounts of data between racks, boards and modules quickly, efficiently and at low cost. Connectivity is thus a key factor, and it is today well understood that electrical cables and low cost commodity hardware cannot accommodate this explosion of required bandwidth. The “infiltration” of photonics in data-centers is already evident and optical interconnects tend to replace electrical cables over shorter and shorter lengths: starting from rack‐to‐rack connectivity, active optical cables are available in a rapidly growing market. Moving to shorter distances, optical interconnects will ultimately penetrate into board‐level to provide chip‐to-chip connectivity. To reach Tb/s capacities an integration technology capable of serial ultra-high speed modulation is believed today to be the missing piece.

POLYSYS was conceived in 2009 with the aim to develop transmitters and receivers for serial 100 Gb/s connectivity based on simple OOK format. The motivation behind its concept was to address the development of technical solutions for high-speed connectivity in data-center environments (chip-to-chip interconnects and rack-to-rack interconnects) and metro networks, but from a more general point of view, also to the development of the underlying technology for high-speed operation of optical and electronic components of optical transceivers in general. In order to address this challenge, POLYSYS invested on electro-optic (EO) polymer platform, not only as the basis for high-speed modulators but also as the basis for more complex photonic integrated circuits, on InP photonic platform as the basis for high-speed photo-detection, on InP-DHBT technology as the basis for high-speed electronics and on the development of a co-design methodology for the integration of these functionalities in small form factor arrayed modules.

POLYSYS has been aiming to provide the disruptive solution to realize for the first time serial 100 Gb/s direct connectivity in datacom and telecom systems. POLYSYS has been developing photonic and electronic components operating at 100 Gb/s based on electro‐optic polymer modulators, InP photodiodes and InP electronics.

The technical objectives of POLYSYS have been aimed through the use of hybrid integration for the assembly of the different components and the use of advanced packaging methodologies for the final packaging of the modules and systems. More specifically, the modules that have been targeted include:

  • Module 1: a 100 Gb/s transmitter
  • Module 2: a 100 Gb/s receiver
  • Module 3: an arrayed 2×100 Gb/s transmitter
  • Module 4: an arrayed 4×100 Gb/s receiver
  • Module 5: a 100 Gb/s transmitter with wavelength tunability and
  • Module 6: a 100 Gb/s receiver with clock-recovery functionality.

The six modules are combined for developing three systems that address the following applications:

  • System 1: on board (chip-to-chip) optical interconnects
  • System 2: rack-to-rack interconnects based on active optical cables and
  • System 3: 100 Gb/s transceivers for rack-to-rack interconnects through optical circuit switches and metro-applications

 

Main Scientific and technical (S&T) results and foregrounds

To accomplish its objectives, POLYSYS based the organisation of the necessary management and RTD around 7 work-packages (WPs) as shown in Figure 1 below.

Figure 1: Structure of Work in POLYSYS Project.
Figure 1: Structure of Work in POLYSYS Project.

Work Package 2: System design and methodology for integration and packaging processes

Activities in WP2 aimed at the exchange of technical information among partners, at defining the system-level specifications of POLYSYS components, at identifying the critical interfaces between individual components and confirming their compatibility, at generating the device models for system-level simulations of POLYSYS systems, at defining the methodology of the integration and packaging procedures and at performing preliminary evaluation of precursor units and test structures in order to refine the specifications of POLYSYS components.

During the course of the project, WP2 has offered a forum for defining the system specifications of POLYSYS components, devices and systems, for aligning the specifications of POLYSYS components and ensure their compatibility, for defining the integration methodologies taking into account the specific characteristics of the different integration platforms, and for making simulation studies regarding the system performance of POLYSYS devices and systems. WP2 has also taken care of a smooth transition of all these activities into WP5 at the final stages of the project.

 

Work package 3: Monolithic polymer and InP-to-polymer integration

WP3 focused on the design and the fabrication of the passive structures on the polymer platform (bent waveguides, MMI couplers, Bragg-gratings), the fabrication of the modulators on the same electro-optic substrate, the development of the butt-coupling technique for the integration of the III-V elements to the polymer platform, and the final delivery of the optical transmitter subassemblies to WP5 for further device assembly.

WP3 has been particularly successful over the total duration of POLYSYS project: work in the framework of the specific workpackage developed the potential and confirmed the potential for monolithic integration of complex photonic structures (such as MMI couplers and Bragg gratings) together with MZM arrays on the EO polymer platform. It also confirmed the potential for hybrid integration of InP elements (laser diodes, gain chips and waveguide-integrated pin photodiodes) with the EO polymer platform using the butt-coupling technique, helping the EO polymer technology mature and evolve from a device specific technology into a general purpose integration platform for photonic integrated circuits (PICs).

Two fabrication runs were executed during the project leading to the optical assembly the 100 Gb/s transmitter (Figure 2) and of the 2×100 GB/s transmitter (Figure 3).

Figure 2: (Left) Photo of the first generation tunable 100 Gb/s transmitter subassembly. (Right) Transmission spectrum at the output of the first generation tunable 100 Gb/s transmitter.
Figure 2: (Left) Photo of the first generation tunable 100 Gb/s transmitter subassembly. (Right) Transmission spectrum at the output of the first generation tunable 100 Gb/s transmitter.
Figure 3: (Left) Photo of the second generation 2×100 Gb/s transmitter subassembly. (Right) Laser spectrum at 25 mA driving current, at the two modulator outputs.
Figure 3: (Left) Photo of the second generation 2×100 Gb/s transmitter subassembly. (Right) Laser spectrum at 25 mA driving current, at the two modulator outputs.

Work-package 4: InP photonics and electronics

WP4 activities were devoted to the design and development of the InP photonic and electronic components. The photonic components included the arrayed (4×100 Gb/s) pin-photodiodes and the arrayed (4×100 Gb/s) pin-photodiodes followed by travelling wave amplifiers (pinTWAs). The electronic components on the other hand included the MUX-DRV circuit that implemented the 2:1 multiplexing and the amplification functionalities, the 1:2 DEMUX circuit (single- and twin-DEMUX circuits) and the clock-and-data recovery (CDR) circuit, all of them being capable of operating at 100 Gb/s line rate.

During the project’s lifetime, in the framework of WP4 quad arrays of pin photodiodes and pinTWA optoelectronic circuits were successfully designed and tested values of bandwidth and conversion gain that render them appropriate for 100 Gb/s operation (Figure 4).

Figure 4: (Left) Mask layout of pinTWA and their explanations on each section. (Right) Photos of fabricated pinTWA after dicing and anti-reflection coating.
Figure 4: (Left) Mask layout of pinTWA and their explanations on each section. (Right) Photos of fabricated pinTWA after dicing and anti-reflection coating.

MUX-DRV circuits (Figure 5) and twin-DEMUX circuits (Figure 6) were designed, fabricated and utilized inside transmitter and receiver modules confirming the potential of both the InP photonics platform of HHI and the InP-DHBT electronics platform of III-V Lab for operation at 100 Gb/s.

Figure 5: (i) Layout of the MUX-DRV (distributed driver part)
Figure 5: (i) Layout of the MUX-DRV (distributed driver part)
Figure 5: (ii) Differential output of the MUX-DRV circuit (distributed version) at: (a) 100 Gb/s, and (b) 112 Gb/s.
Figure 5: (ii) Differential output of the MUX-DRV circuit (distributed version) at: (a) 100 Gb/s, and (b) 112 Gb/s.
Figure 6: Microphotograph of two twin DEMUX circuits.
Figure 6: Microphotograph of two twin DEMUX circuits.

The progress on the design and the fabrication of the individual blocks of the clock-and-data-recovery (CDR) circuit was very significant, although the final circuit was not fabricated as an integrated circuit.

 

Work Package 5: Photonic packaging and system integration

Activities in WP5 were devoted to the integration of the individual components and the final packaging of POLYSYS modules. The partners that perform these activities (TEO and HHI) gathered the optical sub-assemblies (from the polymer group and the receiver group of HHI) and the electronic parts (from III-V Lab) and assembled these parts inside well-designed packages. The packaged modules were forwarded to ICCS/NTUA for system-level testing.

Methodologies for the design of 100G electrical interconnects, the thermal and the mechanical management inside the packages and the optical coupling (between optical chips or to/from optical fibers) were developed and successfully validated. For the first time, integrated 100G transmitters, arrayed 100G transmitters and arrayed 100G receivers were successfully integrated and packaged inside small boxes. Finally, for the first time different polymer platforms were successfully integrated for the development of tunable, high-speed transmitters. This is a major achievement with large potential also for coherent communication systems.

By the end of the project, six modules were packaged and forwarded to WP6 for system testing:

1) the 100Gb/s transmitter (Figure 7)

Figure 7: Prototype of 100 Gb/s transmitter delivered by TEO.
Figure 7: Prototype of 100 Gb/s transmitter delivered by TEO.

2) the 2x100G Tx (Figure 9)

3) the tunable 100G Tx,

4) the 100G integrated optical interconnect (Figure 8)

Figure 8: Prototype of 100 Gb/s integrated optical interconnect.
Figure 8: Prototype of 100 Gb/s integrated optical interconnect.

5-6) two versions of 4x100G pin-DEMUX Rx (Figure 9

Figure 9: (Left) Photograph of the 2x100 Gb/s transmitter that was successfully assembled and packaged by TEO in P3 of POLYSYS. Inside the package the components that have been integrated include a DFB laser, an EO polymer chip with an MMI coupler and two MZMs, and two MUX-DRV circuits. (Right) Photograph of the 4x100G pin-DEMUX receiver that was successfully assembled and packaged by HHI in P3 of POLYSYS. Inside the package the components that have been integrated include a quad array of un-terminated pin-photodiodes and two twin-DEMUX circuits.
Figure 9: (Left) Photograph of the 2x100 Gb/s transmitter that was successfully assembled and packaged by TEO in P3 of POLYSYS. Inside the package the components that have been integrated include a DFB laser, an EO polymer chip with an MMI coupler and two MZMs, and two MUX-DRV circuits. (Right) Photograph of the 4x100G pin-DEMUX receiver that was successfully assembled and packaged by HHI in P3 of POLYSYS. Inside the package the components that have been integrated include a quad array of un-terminated pin-photodiodes and two twin-DEMUX circuits.

Work package 6: System testing and evaluation

The main objective of WP6 was the development of the necessary system testbeds and the evaluation of the system-level performance of the POLYSYS devices, as soon as these devices were made available from the WP5.

ICCS/NTUA designed and prepared the main test-beds for the operation and system-level characterization of POLYSYS modules and systems. The design of the testbeds took into account the system-level specifications of the POLYSYS modules; mainly the required amplitude levels at the input of the electronic components and the amplitude levels at their output. Figure 10 presents the main testbed design for the evaluation of a 100 Gb/s transmitter (tunable or not) and a 100 Gb/s receiver. It was based on the use of a single signal generator as a common reference and a multitude of electrical components such as frequency dividers, frequency doublers, passive splitters, phase shifters and attenuators in order to distribute or collect and assess the electrical data and clock signals to/from the devices under test.

Figure 10: Testbed for system-level evaluation of POLYSYS 100 Gb/s transmitters and receivers.
Figure 10: Testbed for system-level evaluation of POLYSYS 100 Gb/s transmitters and receivers.

The extension of the testbed has been designed in order to facilitate the simultaneous testing of arrayed transmitters (2×100 Gb/s transmitters) and receivers (4×100 Gb/s) through the additional splitting and amplification of the input signals.

Figure 11: Indicative eye-diagrams at 80 and 100 Gb/s using the 2x100G Tx and the 4x100G pin-DEMUX Rx over SMF links.
Figure 11: Indicative eye-diagrams at 80 and 100 Gb/s using the 2x100G Tx and the 4x100G pin-DEMUX Rx over SMF links.

The designed testbeds and the specified evaluation methodology were used for the assessment of the system-level performance of the five modules that were packaged. The performance of the four among these five modules  (2x100G Tx, tunable 100G Tx, two versions of 4x100G pin-DEMUX receivers) was found to be very high and appropriate for 80G and 100G connectivity over dispersion uncompensated links of single mode fibers in intra-data-center environments.

 

Work package 7: Applicability, techno-economical assessment and integration standardization

The major objectives of WP7 were to:

  • Generate and protect intellectual property (patents portfolio) to set the basis for potential commercialisation of the products relevant to the project outcomes.
  • Disseminate project results through website, press releases, publications in scientific journals, presentations at international conferences and workshops as well as through lectures presented in academia, industry and to EU policy makers.
  • Coordinate activities towards possible contributions to standardization bodies.
  • Interact with other EU and national projects.
  • Provide input to industry based on technical work produced/performed in the framework of the project.

In the framework of WP7 a techno-economic analysis was performed for the identification of the most suitable application areas for POLYSYS technology. Specific industrialization plans were also defined and started getting materialized through the industrial collaboration between HHI and GigOptix. Strong bilateral collaboration links were established between other partners, too, and continuation of the collaboration of partners as a consortium was secured through the funding of a follow-up research project. Dissemination activities were intense and comprised a variety of means and channels including scientific publications, participation in workshops, booths, press-releases, and dissemination through the web-site of the project. The visibility of the project was very high, not only in Europe but also in the US, in part due to the participation of GigOptix in POLYSYS consortium.

 

Impact

POLYSYS exploitation plan relies on the fact that serial technologies have always overtaken more complex parallel approaches. POLYSYS has developed photonic and electronic components operating directly at 100 Gb/s, and using arrayed versions of these components has demonstrated 200 and 400 Gb/s connectivity. This is expected to have a disruptive effect in the current development curve of 100G systems that rely on 10×10 Gb/s or 4×25 Gb/s components (mainly for datacom applications).

The achievement of the challenging objectives of POLYSYS brings Europe at the forefront of 100G photonic/electronic component market. Through the exploitation of the project results, POLYSYS partners will be in the position to offer a technology solution with unmatched and directly transfer this technology to coherent transmission systems for metro- and core-network applications based on high-capacity/high flexibility transceivers.

 

The Project’s Public web-site: (www.ict-polysys.eu)

The public website of POLYSYS Project website played a key role to the dissemination and the exploitation of the project results. The website was designed to fulfill the following objectives:

  1. To present the profile of POLYSYS to the visitors of the site (members of the scientific community, people from industry, general public).
  2. To efficiently present the POLYSYS specific objectives, methodology and progress on the research activities. This targets in particular the members of the scientific community and the people from industry and aims at attracting their interest, increasing the visibility of the project and creating a momentum for POLYSYS technology and prototypes in the next years.
  3. To establish the website as an interesting point of reference from people coming from different scientific fields, i.e. polymer science, high‐speed electronics and optoelectronics and optical communications. To fulfil this, the website has been designed so as to contain information and news from recent developments in these fields and announcements for relevant events (conferences, workshops, etc).
  4. To become a point of reference for the consortium members concentrating the main documents and enabling flow of information between the partners.
  5. To facilitate efficient information flow and submission of documents to the EC.
Figure 12. The home page of POLYSYS' public website.
Figure 12. The home page of POLYSYS' public website.

The importance of the website’s role to the dissemination activities is proven by the fact of the dramatic increase of visitor during the second year of the project’s contractual lifetime (Figure 13). This increase was the result of the overall increase in the project visibility, which was related to the POLYSYS technical achievements and dissemination strategy (journal publications, press-releases, ECOC PDP, promotion of POLYSYS through the GigOptix booths at OFC 2012 and ECOC 2012 exhibitions).

Figure 13: Distribution of entry of new POLYSYS web-site users over time from the beginning of the project till the end of M42 (March 2014).
Figure 13: Distribution of entry of new POLYSYS web-site users over time from the beginning of the project till the end of M42 (March 2014).

The POLYSYS Consortium