Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects

[January 2010 – June 2013]

Project Overview

PLATON aimed to address the size and power consumption bottleneck in Data Centers and High-Performance Computing Systems (HPCS) by realizing chip-scale high-throughput routing fabrics with reduced energy consumption and footprint requirements. It intended to demonstrate Tb/s optical router prototypes for optical interconnects adopting plasmonics as its disruptive technology to reduce size and energy values. To achieve this, PLATON intended to deploy innovative plasmonic structures for switching applications and to develop novel fabrication processes for merging plasmonics with silicon nanophotonics and electronics. The enhanced functionality of PLATON’s platform was utilized to develop and demonstrate Tb/s routing, enabling the penetration of a merged plasmonics/photonics configuration in short-range blade and backplane data interconnects. PLATON’s optical board technology was expected to blend the functional potential of small-footprint, high-bandwidth plasmonic structures and the integration potential of plasmonics with the more mature SOI technology providing a new generation of miniaturized photonic components. Its main objectives span along the fabrication and demonstration of:

  1. a whole new series of 2×2 plasmonic switches with ultra-small footprint, very low power consumption and less than 1μsec switching times,
  2. a low latency, small-footprint 4×4 plasmonic thermooptic switch,
  3. an optically addressable plasmonic 1×2 switch capable of operating at bitrates in excess of 10Gb/s, and
  4. A 2×2 and a 4×4 Tb/s optical routing platforms relying on SOI motherboard hosting the plasmonic switching matrix and the IC header processor for application in optical blade and backplane interconnects.

System-level integration involved the demonstration of the packaged Tb/s routing prototype offering minimum space requirements and up to 1.12Tb/s throughput. Its performance was evaluated in a real WDM 40 Gb/s testbed for optical interconnects.

Summary of project context and objectives

PLATON addressed the interconnect problem in high bandwidth, parallel processing environments, adopting an optical interconnect approach and employing optical components based on surface plasmon polaritons to overcome the traditional shortcomings of optics. PLATON introduced the following innovations:

Innovation 1: Advanced DLSPP waveguide engineering

  • Fiber-pigtailing of DLSPP waveguides: PLATON developed a novel butt-coupling technique that provided the first reported pigtailed DLSPP waveguides.
  • On-Chip Silicon-to-DLSPP coupling: PLATON developed an efficient Si-to-DLSPP coupling technique to enable the hybrid integration of plasmonic waveguide elements on silicon-on-insulator (SOI) boards.
  • Advanced thermo-optic DLSPP waveguides: PLATON enhanced the thermooptic efficiency of plasmonic waveguides by involving dielectric materials (IPG and Cyclomer) of significantly higher thermooptic coefficients with respect to the respective coefficient of the so far used PMMA (at least three times higher).
  • Quantum Dot-doped DLSPP waveguides: PLATON pursued research towards next generation, all-optical high-speed DLSPP switching elements.

Innovation 2: Advanced DLSPP switch modules

  • System-qualified 2×2 DLSPP thermooptic switches: PLATON fabricated the first high-speed, ultra-compact thermooptic DLSPP switches. Three generations of 2×2 DLSPP switching modules realized.
  • System-qualified 4×4 DLSPP packet switching matrix: PLATON fabricated a multi-element 4×4 DLSPP switching matrix.
  • All-optical high-speed 1×2 DLSPP switch: PLATON designed and developed an all-optical DLSPP switch operating in the telecom wavelengths.

Innovation 3: Hybrid integration of Plasmonics/Silicon nanophotonics & electronic ICs

  • CMOS-compatible SOI motherboard for silicon/plasmonic/electronic heterointegration: PLATON developed a CMOS compatible application specific optical board setup that integrated silicon and plasmon waveguide elements.
  • Packaging and Fiber-pigtailing: PLATON developed a multi-fiber array coupling technique based on high-index grating vertical couplers for the straightforward pigtailing of the multiple input and output port waveguides of the hybrid photonic chips.

Innovation 4: Tb/s 2×2 & 4×4 DLSPP-based routing platforms for optical data interconnects

High capacity DLSPP-based optical routing platforms for BladeServer and backplane data interconnects: PLATON integrated the SOI motherboard with the DLSPP switching modules and the IC microelectronic circuit into a single system that performed Tb/s-throughput routing of 40Gb/s optical packets for data interconnect applications.

Main Scientific and technical (S&T) results and foregrounds

To accomplish its objectives, PLATON based the organisation of the necessary management and RTD around 7 work-packages (WPs) as shown in the Figure below.

WP2 – Design and Ongoing Evaluation of PLATON’s Platform

Workpackage objectives

WP2 was concerned with the detailed design of the plasmonic/silicon photonic components and subsystems, the SOI motherboard platform, the IC circuitry and the final Tb/s routing interconnection platform. The main objectives were:

  • To define PLATON’s interconnection and routing specifications
  • To specify the parameters and design the components of PLATON’s subsystems
  • To assess the performance of PLATON’s components and to identify the optimum configurations, through theoretical analysis and numerical simulation.
  • To fabricate and evaluate the system performance of first, state-of-the-art DLSPP and SOI structures
  • To provide the final specifications of the modules to be developed based on the simulation analysis and the performance evaluation of the test structures
  • To design the final platform layout and define the final system level experimental testbed specifications

Progress towards objectives detailed for each task

Design of the optical interconnection routing platform

Blue-print designs and the respective gds files have been generated for both the 2×2 and 4×4 PLATON router platforms. Data traffic formats have been defined and a WDM-based packet formatting was adopted with NRZ data signals at 40Gb/s per wavelength. The process flow for the heterointegration of PLATON’s photonics, plasmonics and electronics elements has been determined and has been also successfully applied in real prototypes. Both the 2×2 and the 4×4 router designs were evaluated by means of simulations with true data traffic patterns. An additional 2×2 router architecture has been designed and had its performance simulated, exploiting a dual-WRR plasmonic switch and leading to 320Gb/s (8x40Gb/s) switching capacity.

Design of Silicon Photonic components and RF/electronic circuitry

Specifications about all necessary non‐plasmonic subsystems and components have been defined and the respective device designs have been produced. In more detail:

8:1 SOI multiplexers have been designed in four different layouts for operation in four different spectral bands within the 1530-1565 nm wavelength window, offering 100GHz channel spacing and 40Gbps NRZ signal operation. 2nd order ring resonator structures were employed in the final layout with ring radii close to 9um and to 12um, equipped with heaters for allowing thermo-optical tuning of their resonances in order to accurately define the operating channels. Following the successful experimental confirmation of the SOI-MUX designs generated, this activity has verified the validity of a custom-made circuit-level simulation tool that optimally bridges electromagnetic simulations with system-level functionality towards designing circuits and subsystems with very low computational power.

Silicon-integrated photodiodes:  An all‐silicon implanted photodetector concept has been utilized for header detection and o/e conversion purposes, as this optimally compromises the router prototype needs for easy, cost-effective integration and low-rate header pulse detection. In this type of photodetectors, the generation of charge carriers relies on linear direct absorption at incorporated defect states, which constitute inter-band energy levels caused by silicon ion implantation. Respective designs have been created exploiting Si-rib waveguide structures and have been subsequently verified by experiments performed on fabricated devices, yielding operation at data rates higher than the 1MHz targeted within PLATON for its packet header sequences.

Passive SOI components: Significant progress has been made in the design of TM SOI waveguide platforms. 340nm height and 400nm width TM SOI waveguides were designed based on the rib waveguide structure and using a 50nm slab region, exploiting an 800nm SOG coating. Propagation losses of this layout were finally measured to be 1.5dB/cm. TM grating couplers with more than 50nm bandwidth at the 1550nm spectral band were designed, which were predicting a theoretically calculated insertion loss of 3.25dB/coupler and were finally measured to have 3.2 dB/coupler.

Electronic Circuitry: The IC circuits required for header detection and control signal generation in the 2×2 and 4×4 router platforms have been designed and their performance has been tested both in simulations as well as in FPGA-board deployments. Successful header detection in RTL and gate-level simulations have been carried out.


Design of plasmonic switching elements

All necessary specifications for the 2×2 plasmonic thermo-optic switches were defined within this task and a range of detailed designs for a variety of plasmonic thermo-optic switching architectures both with PMMA and with Cyclomer loadings have been produced. The switching architecture for state-of-the-art DLSPP configurations using PMMA polymer loading was at first level optimized prior proceeding with the numerical analysis and design with Cyclomer loading towards the optimization of performance when the high thermo-optic coefficient (TOC) polymer is used.

A range of different plasmonic switching structures has been designed and numerically investigated for PMMA loading that has a TOC of -1×10-4. These structures have been:

  • An all-plasmonic 2×2 Mach-Zehnder Interferometric switch
  • A hybrid Si-DLSPP 2×2 Mach-Zehnder Interferometer using Si-based 3dB couplers and PMMA-based DLSPP waveguides only at the two MZI branches.
  • An All-Pass DLSPP Waveguide Ring Resonator (WRR) that can be used as an ON/OFF switch
  • An Add/Drop DLSPP Waveguide Ring Resonator (WRR) utilizing different waveguide gaps at the Add and Drop input ports, optimized for 1×2 switching operation.
  • An Add/Drop DLSPP Waveguide Ring Resonator (WRR) utilizing the same waveguide gaps at the Add and Drop input ports, being in this way suitable for 2×2 switching operation.
  • An All-Pass DLSPP Racetrack Resonator.
  • An Add/Drop DLSPP Racetrack
  • A 2×2 DLSPP Directional Coupler switch (DCS)
  • A 2×2 DLSPP MMI Coupler switch
  • A 2×2 DLSPP Desynchronized Coupler (DSC) switch
  • An All-Pass DLSPP Microdisk switch
  • A 2×2 DLSPP Asymmetric MZI switch (A-MZI) that employed two equal length DLSPP MZI arms, but provided a pi/2 phase difference between the two propagating signals by means of a small section of wider PMMA loading. This layout leaded to high extinction ratio values requiring a phase variation of only pi/2 instead of pi needed in the conventional MZI, allowing in this way for low-loss plasmonic switching within the propagation length of PMMA-loaded SPP waveguides despite its rather low TOC value.
  • A 2×2 DLSPP dual-WRR switch that incorporated two ring structures coupled to two 90o crossing waveguides. This type of switch significantly increased the extinction ratio performance at the two output ports compared to the single-ring switching elements even when using the low TOC PMMA loading, increasing at the same time the 3-dB bandwidth of the resonance peaks and facilitating operation with WDM data packet traffic.

A new type of Long-Range DLSPP waveguides has been theoretically investigated and subsequently designed in detail. This waveguide layout enables increased SPP propagation distances up to a few millimeters allowing for enhanced thermo-optically induced phase effects even when using PMMA loadings, however it required a different material structure with two material layers below the gold film.

Cyclomer has been finally decided to be the high TOC polymer of choice. The same set of plasmonic switching structures investigated for PMMA loadings has been also designed for Cyclomer-loading, whose TOC value has been measured to be -2.95×10-4 K-1 at 250nm processing, i.e. almost three times higher than PMMA’s respective coefficient.

The numerical analysis for Cyclomer-loaded plasmonic switches revealed that the 2×2 dual-WRR, the Si-plasmonic MZI and the A-MZI switch design can offer the expected performance for PLATON’s routing platforms. MMI switches can also in principle provide high-quality switching, having however increased sensitivity to fabrication inaccuracies.

Development and system-level routing performance analysis of first interconnected test structures

The first proof of the data capture of PMMA-loaded SPP structures integrated on a SOI waveguide platform has been demonstrated with the following experiments:

  • Single Channel Transmission: The transmission performance of a 60μm-long straight PMMA- ‐loaded SPP waveguide that was hosted in a Si-plasmonic chip was initially assessed in a 10Gb/s 27-1 NRZ transmission experiment. The successful 10Gb/s data transmission over the 60μm-long plasmonic waveguide was verified by Bit Error Rate (BER) measurements, exhibiting error-free operation with negligible power penalties (<0.2dB) compared to the B2B performance.
  • OTDM Signal Transmission: The transmission performance of the 60μm-long straight plasmonic waveguide was evaluated at 160Gb/s serial data rates by using the OTDM technique for multiplexing sixteen 10Gb/s 27-1 RZ signals. Error-free operation was verified for all sixteen 10Gb/s channels that were well-confined within 1dB receiver’s powerrange and exhibited power penalty values ranging from 0 to 0.5 dB against the B2B measurements. Therefore, the signal’s propagation through the DLSPP section was performed without degradation on time and frequency domains demonstrating the efficiency of plasmonics for the transmission of signals that occupy very large bandwidth.
  • WDM Signal Transmission: The transmission performance of the straight PMMA-based waveguide was also evaluated in even higher data rates by multiplexing 12 channels based on the WDM technique for a total throughput of 480Gb/s, considering 200GHz channel spacing and 40Gb/s 231-1 NRZ line‐ Error-free operation with 10-12 BER values was obtained for six out of the twelve channels, with their power penalty ranging between 0.2 and 1 dB against the B2B measurements. The remaining six channels exhibited an error-floor at 10-7 due to their spectral position, since their wavelengths were not located within the flat spectral band of the TM grating couplers experiencing in this way higher losses. Even so, this experiment has validated for the first time the WDM data carrying and signal integrity credentials of DLSPP waveguides.

This task has also demonstrated experimentally a novel power monitoring concept for optical signals at telecom wavelengths with a responsivity of 1.8 μV/μW at λ = 1525 nm for 1V bias voltage.



  • 2×2 and 4×4 silicon-plasmonic router architectures and respective designs
  • Significant impovements in low-loss TM SOI waveguide platform and grating coupler designs
  • A great range of DLSPP plasmonic switch designs, both with PMMA and Cyclomer loadings
  • Data carrying and signal integrity credentials of DLSPP waveguides through single-channel and WDM channel transmission experiments, up to 0.48Tb/s

WP3 – SOI platform and RF/IC circuitry development


Workpackage objectives

This workpackage dealt with the development and fabrication of the SOI optical board, where the active and passive devices were mounted and assembled. The main objectives were:

  • Fabrication and testing of silicon to DLSPP interfaces
  • Development of SOI photonic circuitry
  • Hybrid integration of low-rate photodiodes on SOI motherboard
  • Design and Development of RF circuitry
  • Design and Development of logic ICs


Progress towards objectives detailed for each task

Fabrication and testing of silicon to plasmonic interfaces

Si-to-DLSPP interfacing structures have been designed and developed based on a butt-coupling approach. Several structures relying on the Si-rib waveguide platform were deployed and characterized, revealing an average insertion loss of 2.5dB when a gap of 500nm is exploited between the SOI and the DLSPP waveguide. Theoretical analysis showed that this value can go down to 1dB if no gap is used between the SOI and the DLSPP waveguide.


Fabrication and characterization of logic ICs

A prototype of the ASIC to be employed in the PLATON Router has been fabricated (Fig. 1-5) by AMS using 0.35um CMOS technology and was then evaluated. The process featured four metal layers for interconnects, two polysilicon layers for gate electrodes and interconnects, high resistivity polysilicon structures and output buffers with output voltage up to 3.3V and current of 24mA.

The Project’s Public web-site: (

The BIOFOS website (http://www.ict‐ is updated on a regular basis with publications, press releases, news about recent achievements within BIOFOS. Apart from the public area of the web‐site, the private area continued to be the point of reference for partners regarding the exchange of working documents, reports (deliverables), presentations (such as the PPR2 final presentation, presentations of the SC meetings etc.), meeting minutes etc.

The visibility of the BIOFOS website exhibits a continuous increase as shown in Figure 8, where the evolution of the number of unique visitors from the beginning of the web‐site operation till March 2017, is presented.

The BIOFOS Consortium